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Verilog Tutorial 1

What is verilog?
Verilog is very popular Hardware Description Language (HDL). The other one is VHDL. HDL are used by ASIC designers at frontend level. There are four abstraction level of Verilog:

Verilog can be used for both design and verification purposes. For design verilog code must be synthesizable. However for test bench you can write non-synthesizable verilog codes. Lately, verilog has become obsolete language from verification point of view. Specman and SystemVerilog are widely being used.

Verilog code
Structural: assign a = b & c | d; //Synthesized to gates
Procedural: always@(posedge clk) count <= count + 1; //Synthesized to flops
initial begin clk = 0; end //not Synthesizable
Never assign a wire inside procedural block. If procedural block contains more than 1 statements then they must be within begin-end or fork-join block. Statements within begin-end are always executed sequentially. Combi logic can be implemented using procedural codes. For that, each input should be part of sensitivity list and all the control path to output must be exercised.

fork-join
Statements within fork-join are non-blocking (Parallel) but fork-join as a whole is blocking (sequential). You can have being-end within fork-join also. Structural code are synthesized to gates. Procedural codes are synthesized to flops. Procedural codes are C-like. Beware of race condition in multiple always block.
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