SestemVerilog 1
What is SystemVerilog?SystemVerilog is combined HDL (Hardware Description Language) and HVL (Hardware Verification Language). That means you can have both design and test bench in same language. SystemVerilog has lots of verification capabilities very similar to other HVLs like "e", VERA etc. IEEE has accepted SystemVerilog as standard.
Data Types
Integer data types can be 2-state or 4-state. 2-state takes value either 0 or 1. 4-state can take value 0, 1, X or
Z. 2-state variables takes less memory and simulate faster.
2 state value integer data types are
* shortint : 16-bit signed integer.
* int : 32-bit signed integer.
* longint : 64-bit signed integer.
* byte : 8-bit signed integer, can be used for storing ASCII charater.
* bit : User defined vector types.
4-state value integers data types are
* logic : User defined vector types.
* reg : User defined vector types.
* wire : User defined vector types.
* integer : 32-bit signed integer.
* time : 64-bit unsigned integer.
String data types are dynamic in nature and are used to store strings
Str1 == Str2; Equality
Str1 != Str2; Inequality
<,>,<=,=> Comparison
{Str1, Str2,...,Strn}; Concatenation
{n{str}}; Replication
Str.method( ); Function Call